Semiconductors & Chipmaking · Projected milestone

Chips designed end to end by AI

Estimated year~2029

70% by 2032 · including earlier years

The year is an editorial timing estimate. The percentage applies to occurrence by the stated deadline. These estimates are not calibrated odds.

AI agents design, verify and lay out complete processors with only a handful of human engineers.

Explore this milestone on the interactive map

What the forecast means

Milestone stage: demonstration

partially-demonstrated

Autonomous design/debug/implementation components exist; the complete processor workflow remains unconfirmed.

Completion criteria: Publish the requirements, human-work log, verification coverage, physical signoff and fabricated-chip results. A small educational core may establish a precursor but the resolving processor must deliver a useful independently measured application workload.

This page describes a forecast, rather than an achieved result. Read the methodology and assumptions.

Built on

AI chip-layout toolsRecorded · 2021enables
Autonomous AI agentsRecorded · 2025enables
Expert-level general AIForecast · ~2028influences

Led to

Chips that design successorsForecast · ~2033requires
AI-invented transistor typeForecast · ~2036enables
Near-zero-energy computingForecast · ~2058enables

Sources & evidence

Synopsys advances agentic AI chip design with AMD and Microsoft 2026-07-27
Synopsys announces autonomous debug and implementation workflows available for evaluation, with AMD evaluating them. These are important design-workflow components, not a verified complete novel processor tape-out by an autonomous team.
Cadence expands ChipStack with RTL generation and early PPA optimization 2026-09-22
Cadence announces specification-to-RTL generation and verification/optimization with early customer evaluation. Vendor-reported block-level quality is not evidence that whole-chip physical validation and all signoff are solved.

Record reviewed 2026-10-18